A programmable logic device is generally configured by storing configuration data in its configuration memory. The configuration memory then provides signals based on the configuration data to control circuit elements (e.g., multiplexers) that determine the function and operation of the programmable logic device (e.g., a field programmable gate array, a complex programmable logic device, or a programmable interconnect device).
For example, FIG. 1 illustrates a conventional six-transistor memory cell (also referred to as a static random access memory (SRAM) cell), which is used to store one bit of configuration data. These types of memory cells are distributed throughout the programmable logic device to form columns of configuration memory, which are connected by complementary pairs of data lines (also referred to as bit lines and labeled DATA and DATAN in FIG. 1). The data lines in each column provide a data path to allow data to be written to (also known as configuring or programming) and read from the memory cells in that column. For a large programmable logic device, the data lines may be thousands of microns long and connect thousands of the memory cells.
In terms of general operation for the memory cell of FIG. 1, data (e.g., one configuration bit) may be transferred to and from the memory cell by switching on two of its six transistors (labeled access devices) with an address line. During a read operation, the data lines (DATA, DATAN) are generally pre-charged to a high voltage state before the access devices for the memory cell are switched on. When the access devices are switched on, the memory cell pulls the DATA line or the DATAN line low, which indicates that a zero or a one, respectively, is stored in the memory cell.
During a write operation, one of the data lines is driven high while the other data line is driven low, depending upon whether a zero or a one is to be stored in the memory cell. The access devices are then switched on by the address line and the state of the memory cell is set based upon the voltage levels of the data lines. During a read or a write operation of the memory cell, the access devices to the other memory cells in the column are switched off to avoid unintended reading or writing to those memory cells.
A drawback of conventional columns of configuration memory is that high parasitic resistance and capacitance from the data lines, along with the combined leakage current from all of the un-accessed memory cells that are on the same data lines, may cause a significant voltage drop from source to destination (e.g., from memory cell to read sensing circuit or from data input buffer to memory cell). The voltage drop may decrease the stability of the memory cell being accessed and result in errors or difficulty in reading or writing to large programmable logic devices.
Conventional techniques to address this problem, such as over-designing for the stability of the memory cell, add significant circuit area and/or lower the expected quality and yield, while increasing the complexity of the programmable logic device. As a result, there is a need for improved techniques to read and write data to memory within a programmable logic device.